1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, and more particularly, to a nonvolatile semiconductor memory device including a memory cell transistor and a select transistor for storing information by drawing electrons from a floating gate by means of a tunnel phenomenon.
2. Description of the Background Art
An EEPROM (Electrically Erasable and Programmable Read Only Memory) that can program data arbitrarily and that can electrically write/erase information is known as one typical type of a nonvolatile semiconductor memory device. An EEPROM is advantageous in that writing and erasing can both be carried out electrically. However, because two transistors are required in a memory cell, it was difficult to increase the integration density. A flash EEPROM is proposed that has a memory cell formed of one transistor, and that can electrically erase written information globally. Such a flash EEPROM is disclosed in, for example, U.S. Pat. No. 4,868,619.
Furthermore, a DINOR (Divided Bit Line NOR) type cell is proposed as a nonvolatile semiconductor memory device that realizes various problems for a flash memory such as low cost, low voltage and low power consumption, high speed writing, sector erasure (independent partial erasure), and high reliability. The details of such a DINOR type cell is disclosed in IEDM, 1992, pp. 599-602, for example. A DINOR type cell employs a main/sub-bit line structure in a conventional NOR type cell with a select gate.
FIG. 9 is a sectional view of a conventional proposed DINOR type cell. FIG. 10 is an equivalent circuit diagram showing the array structure of a conventional DINOR type cell. Referring to FIG. 9, 8 bits (8 cells) of memory cell transistors 110 are formed with a predetermined distance therebetween in a conventional DINOR type cell. A select transistor 103 is formed so as to be adjacent to memory cell transistor 110. A sub-bit line 102 is formed to electrically connect the 8 bits of memory cell transistors 110.
A main bit line 101 is formed connected to select transistor 103. A word line 104 is provided above main bit line 101 with a predetermined distance therebetween. A DINOR type cell of the above-described structure can achieve low voltage-low power consumption and high speed writing by modifying the electron injection mechanism to a mechanism that employs FN (Fowler-Nordheim) tunneling phenomenon. Low cost and sector erasure are realized by employing a main/sub-bit line structure and by using a select gate. The problem of drain-disturb phenomenon that occurs in the erasure operation of each sector is eliminated due to the usage of a select gate. The operation speed is as high as that of a conventional flash memory.
As shown in FIG. 10, a conventional DINOR type cell has the number of second aluminum interconnections (word lines) 104 reduced to half the number of control gates (word lines) 120 by connecting a control gate (word line) symmetrically sandwiching a select gate (or an element isolation region). Therefore, the pitch of a second aluminum interconnection (word line) 104 that has a large minimum pitch according to the limitation of a manufacturing process can be made double that of control gate 120. As a result, connection (shunt) between second aluminum interconnection 104 and control gate 120 can be implemented easily.
However, the above structure had a problem that an additional region for connecting the two symmetrically positioned control gates (word lines) 120 is required to prevent increase in the integration density. It was also difficult to further reduce the cell size in a conventional DINOR type cell having 8 memory cells connected to each bit line 102.